Wednesday, October 3, 2012

Viva and Written Question For the Post ASIC Design Enginner

Viva and Written Question For the Post ASIC Design Engineer

Q. What is meant by scaling in VLSI design? Describe various effects of scaling.
Q. What is meant by 90nm technology?
Q. What is a transmission gate, and what is its typical use in VLSI?
Q. What is ASIP?
Q. What are the different design styles in VLSI?
Q. What are the differences between gate array ASIC and cell-based ASIC?
Q. When you want the production in the bulk amount which design style you prefer? Justify?
Q. What is EDIF? Explain?
Q. State the importance of Lithography in VLSI design?
Q. Define Baud rate?
Q. What is the relation between DBM and DB?
Q. What do you mean by technology in VLSI design?
Q. What is the technology used in P IV?
Q. What is superscalar architecture?
Q. How do you tackle coupling when design deep submicron SRAM memories?
Q. Power Optimization Techniques for deep sub-micron?
Q. For CMOS logic, give the various techniques you know to minimize power consumption
Q. What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus
Q. Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
Q. In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
Q. Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
Q. Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram
Q. Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
Q. For an NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
Q. What happens if we increase the number of contacts or via from one metal layer to the next?
Q. Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
Q. How does Resistance of the metal lines vary with increasing thickness and increasing length?
Q. What are the limitations in increasing the power supply to reduce delay?
Q. What happens to delay if we include a resistance at the output of a CMOS circuit?
Q. What happens to delay if you increase load capacitance?
Q. Give the expression for calculating Delay in CMOS circuit
Q. Give the expression for CMOS switching power dissipation
Q. How do you size NMOS and PMOS transistors to increase the threshold voltage?
Q. Explain sizing of the inverter
Q. What is a SoC (System On Chip), ASIC, “full custom chip”, and an FPGA?
Q. What is ASIC design flow?
Q. What is “Scan” ?
Q. What are RTL, Gate, Metal and FIB fixes? What is a “sewing kits”?
Q. How do you measure the size and density of various programmable logic devices?
Q. What is soft processor? What is hard processor?
Q. What is meant by 90nm technology?
Q. What do you mean by translation and mapping?
Q. What is Back annotation?
Q. What is DRC and LVS and name some tools which are used for these operations?
Q. What is electron migration?
Q. What are the goals of partitioning?
Q. Differentiate Global routing and detailed routing?
Q. What is floor planning? (goals and objectives)
Q. What is the exact difference between floor planning and placement?
Q. Define congestion in routing?
Q. What do you mean by rip-up and re-routing?
Q. What is Yield in fabrication process?
Q. What is the difference between ASIC Design and FPGA Design?
Q. What is floating gate transistor?
Q. Write the characteristics of a cell in a standard cell library?
Q. What is Meta-stability state?
Q. Setup time and hold time in digital circuits.
Q. False path in FPGA’s, Critical path, Negative slack, Jitter vs. clock skew .
Q. Routing delay, Flop to out delay, Flop to flop delay, Pad to flop delay, Board delay.
Q. Knowledge of Synthesis and layout constraints.